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<p>This typedef contains all the configuration feilds which must be set before the start of the data transfer.  
 <a href="struct_x_csu_dma___configure.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:a524260e03c75bc8745da0e4b7dca71ed"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#a524260e03c75bc8745da0e4b7dca71ed">SssFifoThesh</a></td></tr>
<tr class="memdesc:a524260e03c75bc8745da0e4b7dca71ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">SSS FIFO threshold value.  <a href="#a524260e03c75bc8745da0e4b7dca71ed">More...</a><br/></td></tr>
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<tr class="memitem:a7ca88dbe204c7b24ce7e529da53e1ae2"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#a7ca88dbe204c7b24ce7e529da53e1ae2">ApbErr</a></td></tr>
<tr class="memdesc:a7ca88dbe204c7b24ce7e529da53e1ae2"><td class="mdescLeft">&#160;</td><td class="mdescRight">ABP invalid access error.  <a href="#a7ca88dbe204c7b24ce7e529da53e1ae2">More...</a><br/></td></tr>
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<tr class="memitem:a4d1217d471a558f54534c15213bbb264"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#a4d1217d471a558f54534c15213bbb264">EndianType</a></td></tr>
<tr class="memdesc:a4d1217d471a558f54534c15213bbb264"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of endianness.  <a href="#a4d1217d471a558f54534c15213bbb264">More...</a><br/></td></tr>
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<tr class="memitem:a1aeadd99f4f96da636b9cb0c2be21c09"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#a1aeadd99f4f96da636b9cb0c2be21c09">AxiBurstType</a></td></tr>
<tr class="memdesc:a1aeadd99f4f96da636b9cb0c2be21c09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of AXI bus.  <a href="#a1aeadd99f4f96da636b9cb0c2be21c09">More...</a><br/></td></tr>
<tr class="separator:a1aeadd99f4f96da636b9cb0c2be21c09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af2b9f211561ad313b726a60104afc32e"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#af2b9f211561ad313b726a60104afc32e">TimeoutValue</a></td></tr>
<tr class="memdesc:af2b9f211561ad313b726a60104afc32e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time out value.  <a href="#af2b9f211561ad313b726a60104afc32e">More...</a><br/></td></tr>
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<tr class="memitem:af17af84045f926ff8e386509cc0c9aee"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#af17af84045f926ff8e386509cc0c9aee">FifoThresh</a></td></tr>
<tr class="memdesc:af17af84045f926ff8e386509cc0c9aee"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO threshold value.  <a href="#af17af84045f926ff8e386509cc0c9aee">More...</a><br/></td></tr>
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<tr class="memitem:a984f69d8fa925618e85800ba8fd2d155"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#a984f69d8fa925618e85800ba8fd2d155">Acache</a></td></tr>
<tr class="memdesc:a984f69d8fa925618e85800ba8fd2d155"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI CACHE selection.  <a href="#a984f69d8fa925618e85800ba8fd2d155">More...</a><br/></td></tr>
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<tr class="memitem:ac6f8c811d5b1ecf86d37091fc132717e"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#ac6f8c811d5b1ecf86d37091fc132717e">RouteBit</a></td></tr>
<tr class="memdesc:ac6f8c811d5b1ecf86d37091fc132717e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Selection of Route.  <a href="#ac6f8c811d5b1ecf86d37091fc132717e">More...</a><br/></td></tr>
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<tr class="memitem:a2f45ba702e0487ed32152186339d7052"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#a2f45ba702e0487ed32152186339d7052">TimeoutEn</a></td></tr>
<tr class="memdesc:a2f45ba702e0487ed32152186339d7052"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable of time out counters.  <a href="#a2f45ba702e0487ed32152186339d7052">More...</a><br/></td></tr>
<tr class="separator:a2f45ba702e0487ed32152186339d7052"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a00365f4d0973fcb3fd39382312775748"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#a00365f4d0973fcb3fd39382312775748">TimeoutPre</a></td></tr>
<tr class="memdesc:a00365f4d0973fcb3fd39382312775748"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pre scaler value.  <a href="#a00365f4d0973fcb3fd39382312775748">More...</a><br/></td></tr>
<tr class="separator:a00365f4d0973fcb3fd39382312775748"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acdf6a30da74f891648e17d1ce9bfadae"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html#acdf6a30da74f891648e17d1ce9bfadae">MaxOutCmds</a></td></tr>
<tr class="memdesc:acdf6a30da74f891648e17d1ce9bfadae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of outstanding commands.  <a href="#acdf6a30da74f891648e17d1ce9bfadae">More...</a><br/></td></tr>
<tr class="separator:acdf6a30da74f891648e17d1ce9bfadae"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>This typedef contains all the configuration feilds which must be set before the start of the data transfer. </p>
<p>All these feilds of CSU_DMA can be configured by using XCsuDma_SetConfig API. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a984f69d8fa925618e85800ba8fd2d155"></a>
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          <td class="memname">u8 XCsuDma_Configure::Acache</td>
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<p>AXI CACHE selection. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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          <td class="memname">u8 XCsuDma_Configure::ApbErr</td>
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<p>ABP invalid access error. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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          <td class="memname">u8 XCsuDma_Configure::AxiBurstType</td>
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<p>Type of AXI bus. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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          <td class="memname">u8 XCsuDma_Configure::EndianType</td>
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<p>Type of endianness. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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          <td class="memname">u8 XCsuDma_Configure::FifoThresh</td>
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<p>FIFO threshold value. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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          <td class="memname">u8 XCsuDma_Configure::MaxOutCmds</td>
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<p>Maximum number of outstanding commands. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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          <td class="memname">u8 XCsuDma_Configure::RouteBit</td>
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<p>Selection of Route. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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          <td class="memname">u8 XCsuDma_Configure::SssFifoThesh</td>
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<p>SSS FIFO threshold value. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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<a class="anchor" id="a2f45ba702e0487ed32152186339d7052"></a>
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          <td class="memname">u8 XCsuDma_Configure::TimeoutEn</td>
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<p>Enable of time out counters. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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          <td class="memname">u16 XCsuDma_Configure::TimeoutPre</td>
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<p>Pre scaler value. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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<p>Time out value. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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